The present invention relates to semiconductor static random access memories (SRAMs).
The key desiderata driving SRAM art are speed, density, and power dissipation.
One effective way to improve power dissipation, at little cost in speed or density, has been found to be CMOS processing wherein both n-channel and p-channel active devices are available.
Fabrication constraints for a scaled CMOS process are based on cost related issues, which dictate the minimization of processing steps. Recent studies in CMOS fabrication techniques for 1 micron-2 micron geometry CMOS, have focussed on reduction of latch up sensitivity, and on optimization of the higher gain n-channel transistor for maximum performance.
These issues have led to the development of the "reverse CMOS" or twin-tub process in which a p+/p-type epi substrate is used to fabricate NMOS circuits, with a n-type tank in which the p-channel transistors are fabricated.
MOS static RAMs conventionally are based on 6T cells in which the pass transistors, gated by the word lines, and the active drive transistors are all N-channel. Typically, the loads have been high-resistance polysilicon resistors or, in NMOS, depletion devices; that is, they have been high-impedance devices, designed to conduct little current from the high node of the cell, in order to limit power consumption, while still being able to at least hold up the high side of the cell.
In CMOS RAMs, the load devices have been P-channel enhancement transistors, which turn off on the low side of the cell because their gates are connected to the high node. This reduces stand-by power considerably. However, when they turn on they hold the high node strongly high. Then they have relatively low impedance even though their widths are minimum and even though their carrier mobility is only about one third that of N-channel devices. Thus, the CMOS cell is not easily disturbed when read by a pair of bit lines initially carrying the opposite potential difference from the previous cycle, nor is the high node so susceptible to being discharged by mobile charge from the tracks of alpha-particles. Also, it does not have excessive standby current at higher temperatures, as may a depletion-load cell whose device Vto's all fall with increasing temperature.
A cell, selected for read by turning on the word line pass transistors, should not have its low node pulled high by a bit line which is constantly precharged high, to a Vt below Vcc; if its other node is pulled high much less strongly because its bit line is low from a previous read or write, the cell could switch. Writing to the cell involves pulling one bit line low; when the pass transistors are on, the corresponding node is pulled low, resisted only by the weak P-channel load device, turning on the other P-channel driver device and switching the cell.
Thus, although such a CMOS 6T cell may be more complex and larger than an NMOS cell, due to the P-type mask with its boundary region, the P-channel load represents an improvement in stability of data retention at N-channel devices as drivers and word-select transistors, so it is not surprising that this is the CMOS cell that has been generally adopted for existing static RAMs.
It is an object of the present invention to provide a static random access memory cell having fast read, fast write, immunity to read and good resistance to alpha-particle induced error. It is a further object of the invention to provide a cell having these advantages which is sensitive to process variations. It is a further object of the invention to provide a cell having these advantages and low power dissipation too.
As taught by the present invention, the other true CMOS 6T cell, which would have N-channel loads and four P-channel transistors, turns out to have unexpected advantages. In this case, the P-channel drive transistors pull up, the bit lines are constantly precharged to a Vt above the lower rail, and the cell is written by pulling one bit line up.
Published P-load cells (four n-channel devices) all seem to have similar device sizes as estimated from micrographs. We may assume that the P-channel conduction factor K' is roughly 1/4 of the N-channel K', neglect the effects of different P+ and N+ source/drain resistances, and define the Beta of a cell to be the ratio of the betas (beta=K' W/L) of the drive and pass transistors. For a PMOS cell having a subthreshold-current-leakage load transistor (which is a passive device somewhat like a resistor), the optimum sizes give a similar result for Beta (the pertinent parameter of the subthreshold load device is its resistance, here 300 MegOhms):
1.5-3 micron bulk CMOS PMOS subthreshold-load cell:
Beta=((4/1.5)/(3/2))=1.8. PA1 Load/Pass=((3/2.5)/(3/2))=0.8. PA1 Drive/Load=((4/1.5)/(3/2.5))=2.2.
This scheme requires that the BIT and BIT lines be precharged near Vss, and that the p-channel pass transistors be turned off if the wordline is held at Vcc nominally. The nominal condition of storage is thus just the opposite of what is used in current art with n-channel pass devices.
According to the present invention there is provided:
A static random access memory comprising:
an array of memory cells arranged in rows and columns, each memory cell comprising two access transistors, two driver transistors, and two load elements, wherein said access transistors and said driver transistors are p-channel field effect transistors;
a plurality of address decoder means, for selecting a particular one of said cells in said array for reading information out of or writing into; and
sense amplifier means for amplifying the output signal provided by a particular one of said cells accessed by said address decoder means;
wherein said access transistors have a width-to-length ratio greater than the width-to-length ratio of said driver transistors.